/* pmu_event_def.h -- define all supported events */

#ifndef __PMU_EVENT_DEF_
#define __PMU_EVENT_DEF_


/* All defined PMU events (add more if needed) */
enum {
    PMU_L1_Data_Cache_Access =0,  /*DATA_MEM_REF, L1 data cache read/write*/
    PMU_L1_Data_Cache_Miss,       /*Approximed by DCU_LINES_IN, L1 data cache miss */
    PMU_L1_Data_Cache_Miss_Cycle, /*DCU_MISS_OUTSTANDING*/ 
    PMU_Other_Stall_Cycle,        /*RESOURCE_STLLS */
    PMU_L2_Data_Cache_Read,       /*L2_LD*/
    PMU_L2_Data_Cache_Write,      /*L2_ST */
    PMU_L2_Cache_Access,          /*L2_RQSTS */
    PMU_L2_Cache_Miss,            /*Approximated by L2_LINES_IN - as PAPI uses*/

    PMU_Mem_Bus_Access,           /*BUS_TRAN_MEM, num of completed memory transactions*/

    PMU_Uops_Retired,             /*UOPS_RETIRED */
    PMU_Inst_Retired,             /*INST_RETIRED */
    PMU_Inst_Decoded,             /*INST_DECODED */
    PMU_Clk_Cycle_Unhalted,       /*CPU_CLK_UNHALTED, is close to TSC? */
    PMU_Ifetch_Stall_Cycle,       /*IFU_MEM_STALL */
    
    PMU_BUS_DATA_RCV,             /*BUS_DATA_RCV: # of bus clk cycles during which, processor is rcving data *//* CANO-2005 */
    /*Add more if needed */
    PMU_MAX_EVENT
};


// defalut values: 0 for counter mask, INV, EN, INT,PC, E; 
//                 1 for OS mode (1<<16), 
//                 1 for USR mode (1<<17)
#define PMU_default   ( 0|(1<<16)|(1<<17))

unsigned int PMU_event[PMU_MAX_EVENT] = {
    PMU_default | 0x43 | (0x00<<8), // PMU_L1_Data_Cache_Access  0 --> I DONT THINK SO!! (CANO)
    PMU_default | 0x45 | (0x00<<8), // PMU_L1_Data_Cache_Miss    1 --> I DONT THINK SO!! (CANO)
    PMU_default | 0x48 | (0x00<<8)|(0x01<<24), // PMU_L1_Data_Cache_Miss_Cycle, >=1 outstanding
    PMU_default | 0xa2 | (0x00<<8), // PMU_Other_Stall_Cycle     3
    PMU_default | 0x29 | (0x0f<<8), // PMU_L2_Data_Cache_Read    4
    PMU_default | 0x2a | (0x0f<<8), // PMU_L2_Data_Cache_Write   5
    PMU_default | 0x2e | (0x0f<<8), // PMU_L2_Cache_Access       6
    PMU_default | 0x24 | (0x0f<<8), // PMU_L2_Cache_Miss         7
    PMU_default | 0x6f | (0x00<<8), // PMU_Mem_Bus_Access        8
    PMU_default | 0xc2 | (0x00<<8), // PMU_Uops_Retired          9
    PMU_default | 0xc0 | (0x00<<8), // PMU_Inst_Retired          10
    PMU_default | 0xd0 | (0x00<<8), // PMU_Inst_Decoded          11
    PMU_default | 0x79 | (0x00<<8), // PMU_Clk_Cycle_Unhalted    12
    PMU_default | 0x86 | (0x00<<8),  // PMU_Ifetch_Stall_Cycle    13

    PMU_default | 0x64 | (0x00<<8)  // PMU_BUS_DATA_RCV          14 /* CANO-2005 */
};

char* PMU_event_name[PMU_MAX_EVENT] = {
  "PMU_L1_Data_Cache_Access    ",
  "PMU_L1_Data_Cache_Miss      ",
  "PMU_L1_Data_Cache_Miss_Cycle",
  "PMU_Other_Stall_Cycle       ",
  "PMU_L2_Data_Cache_Read      ",
  "PMU_L2_Data_Cache_Write     ",
  "PMU_L2_Cache_Access         ",
  "PMU_L2_Cache_Miss           ",
  "PMU_Mem_Bus_Access          ",
  "PMU_Uops_Retired            ",
  "PMU_Inst_Retired            ",
  "PMU_Inst_Decoded            ",
  "PMU_Clk_Cycle_Unhalted      ",
  "PMU_Ifetch_Stall_Cycle      ",

  "PMU_BUS_DATA_RCV            " /* CANO-2005 */
};



#endif // __PMU_EVENT_DEF_