--
--  File: pred_reg_v2.vhd
--  created by Design Wizard: 01/08/02 02:54:01
--

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {pred_reg_v2} architecture {pred_reg_v2_bh}}

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity pred_reg_v2 is
	port (	 
	--		clk: in STD_LOGIC;
		reset: in STD_LOGIC;
		we_L: in STD_LOGIC;
		we_R: in STD_LOGIC;
		--w8b_L: in STD_LOGIC;
		we_8b: in STD_LOGIC;
		wr_banksel: in STD_LOGIC_VECTOR (3 downto 0);
		rd_banksel: in STD_LOGIC_VECTOR (3 downto 0);		 
		imm8: in STD_LOGIC_VECTOR (7 downto 0);
		rd_addr_L: in STD_LOGIC_VECTOR (2 downto 0);
		wr_addr1_L: in STD_LOGIC_VECTOR (2 downto 0);
		wr_addr2_L: in STD_LOGIC_VECTOR (2 downto 0);
		wr_d1_L: in STD_LOGIC;
		wr_d2_L: in STD_LOGIC;
		wr_d1_R: in STD_LOGIC;
		wr_d2_R: in STD_LOGIC;
		rd_addr_R: in STD_LOGIC_VECTOR (2 downto 0);
		wr_addr1_R: in STD_LOGIC_VECTOR (2 downto 0);
		wr_addr2_R: in STD_LOGIC_VECTOR (2 downto 0);
		out_L: out STD_LOGIC;
		out_R: out STD_LOGIC --;
	);
end pred_reg_v2;

--}} End of automatically maintained section

architecture pred_reg_v2_bh of pred_reg_v2 is  
type predreg is array (integer range 0 to 15) of std_logic_vector(7 downto 0);
signal regf : 	predreg;
begin
	  -- <<enter your statements here>>
  pred: process (reset, we_L, we_R, we_8b, wr_banksel, rd_banksel, imm8, 
  				 rd_addr_L, rd_addr_R, wr_addr1_L, wr_d1_L, wr_d1_R, wr_addr1_R,
                 wr_addr2_L, wr_d2_L, wr_d2_R, wr_addr2_R)
    variable pred_regfile : predreg := ("11111111","11111111",
                                        "11111111","11111111",
                                        "11111111","11111111",
                                        "11111111","11111111",
										"11111111","11111111",
                                        "11111111","11111111",
                                        "11111111","11111111",
                                        "11111111","11111111");
--	variable prev_pred8 : std_logic_vector(7 downto 1) := "0000000" ;
    variable wrsel_index, wraddr1, wraddr2, rdsel_index, rdaddr : integer;
	begin 
		 
		if reset = '0' then	 
			-- reset procedure
			pred_regfile := ("11111111","11111111",
                             "11111111","11111111",
                             "11111111","11111111",
                             "11111111","11111111",
							 "11111111","11111111",
                             "11111111","11111111",
                             "11111111","11111111",
                             "11111111","11111111");
--			prev_pred8   :=  "0000000";
		end if;				  
			-- do write if write enable is valid
			-- 8bit write (actually 7bit write because P0 is always '1'
			wrsel_index := to_integer(unsigned(wr_banksel));
			wraddr1     := to_integer(unsigned(wr_addr1_L));	   
			wraddr2     := to_integer(unsigned(wr_addr2_L));
			if we_L = '1' then
				if we_8b = '1' then
					pred_regfile(wrsel_index) := imm8(7 downto 0);
				else
					pred_regfile(wrsel_index)(wraddr1) := wr_d1_L;
					pred_regfile(wrsel_index)(wraddr2) := wr_d2_L;
				end if;	
				pred_regfile(wrsel_index)(0) := '1';
			end if;			 
			
			wrsel_index := to_integer(unsigned(wr_banksel));
			wraddr1     := to_integer(unsigned(wr_addr1_R));
			wraddr2     := to_integer(unsigned(wr_addr2_R));
			if we_R = '1' then
				if we_8b = '1' then
					pred_regfile(wrsel_index) := imm8(7 downto 0);
				else
					pred_regfile(wrsel_index)(wraddr1) := wr_d1_R;
					pred_regfile(wrsel_index)(wraddr2) := wr_d2_R;
				end if;							
				pred_regfile(wrsel_index)(0) := '1';
			end if;											   
			
			-- do read 
			rdsel_index := to_integer(unsigned(rd_banksel));
			rdaddr      := to_integer(unsigned(rd_addr_L));
			if rdaddr /= 0 then
				out_L <= pred_regfile(rdsel_index)(rdaddr);
			else
				out_L <= '1';
			end if;		   
			rdsel_index := to_integer(unsigned(rd_banksel));
			rdaddr      := to_integer(unsigned(rd_addr_R));
			if rdaddr /= 0 then
				out_R <= pred_regfile(rdsel_index)(rdaddr);
			else
				out_R <= '1';
			end if;
			
		regf <= pred_regfile;			
			
	end process;
end pred_reg_v2_bh;