-- -- file d:\My_Designs\PLX_stall_impr\compile\PLX.vhd -- generated Sun Jan 20 17:57:02 2002 -- from d:\My_Designs\PLX_stall_impr\src\PLX.bde -- by BDE2VHDL generator version 1.10 -- library IEEE; use IEEE.std_logic_1164.all; entity PLX is port( clk : in STD_LOGIC; reset : in STD_LOGIC ); end PLX; architecture struc_PLX of PLX is ---- Component declarations ----- component ALU64 port ( Op1 : in STD_LOGIC_VECTOR(63 downto 0); Op2 : in STD_LOGIC_VECTOR(63 downto 0); Opcode : in STD_LOGIC_VECTOR(5 downto 0); SubOP : in STD_LOGIC_VECTOR(7 downto 0); ALUout : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component Ctrl_reg port ( I_Instr_type_L : in STD_LOGIC_VECTOR(8 downto 0); I_Instr_type_R : in STD_LOGIC_VECTOR(8 downto 0); I_Opcode_L : in STD_LOGIC_VECTOR(5 downto 0); I_Opcode_R : in STD_LOGIC_VECTOR(5 downto 0); I_PC_L : in STD_LOGIC_VECTOR(31 downto 0); I_PC_R : in STD_LOGIC_VECTOR(31 downto 0); I_Rd_L : in STD_LOGIC_VECTOR(4 downto 0); I_Rd_M_L : in STD_LOGIC_VECTOR(4 downto 0); I_Rd_M_R : in STD_LOGIC_VECTOR(4 downto 0); I_Rd_R : in STD_LOGIC_VECTOR(4 downto 0); I_Rs1_L : in STD_LOGIC_VECTOR(4 downto 0); I_Rs1_R : in STD_LOGIC_VECTOR(4 downto 0); I_Rs2_L : in STD_LOGIC_VECTOR(4 downto 0); I_Rs2_R : in STD_LOGIC_VECTOR(4 downto 0); I_Subopsw_L : in STD_LOGIC_VECTOR(7 downto 0); I_Subopsw_R : in STD_LOGIC_VECTOR(7 downto 0); I_imm_L : in STD_LOGIC_VECTOR(63 downto 0); I_imm_R : in STD_LOGIC_VECTOR(63 downto 0); I_valid_L : in STD_LOGIC_VECTOR(0 downto 0); I_valid_R : in STD_LOGIC_VECTOR(0 downto 0); I_we_Dcache_L : in STD_LOGIC_VECTOR(0 downto 0); I_we_Dcache_R : in STD_LOGIC_VECTOR(0 downto 0); I_we_RF_L : in STD_LOGIC_VECTOR(0 downto 0); I_we_RF_M_L : in STD_LOGIC_VECTOR(0 downto 0); I_we_RF_M_R : in STD_LOGIC_VECTOR(0 downto 0); I_we_RF_R : in STD_LOGIC_VECTOR(0 downto 0); I_we_pred_L : in STD_LOGIC_VECTOR(0 downto 0); I_we_pred_R : in STD_LOGIC_VECTOR(0 downto 0); I_wr_pred_addr1_L : in STD_LOGIC_VECTOR(2 downto 0); I_wr_pred_addr1_R : in STD_LOGIC_VECTOR(2 downto 0); I_wr_pred_addr2_L : in STD_LOGIC_VECTOR(2 downto 0); I_wr_pred_addr2_R : in STD_LOGIC_VECTOR(2 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; Instr_type_L : out STD_LOGIC_VECTOR(8 downto 0); Instr_type_R : out STD_LOGIC_VECTOR(8 downto 0); Opcode_L : out STD_LOGIC_VECTOR(5 downto 0); Opcode_R : out STD_LOGIC_VECTOR(5 downto 0); PC_L : out STD_LOGIC_VECTOR(31 downto 0); PC_R : out STD_LOGIC_VECTOR(31 downto 0); Rd_L : out STD_LOGIC_VECTOR(4 downto 0); Rd_M_L : out STD_LOGIC_VECTOR(4 downto 0); Rd_M_R : out STD_LOGIC_VECTOR(4 downto 0); Rd_R : out STD_LOGIC_VECTOR(4 downto 0); Rs1_L : out STD_LOGIC_VECTOR(4 downto 0); Rs1_R : out STD_LOGIC_VECTOR(4 downto 0); Rs2_L : out STD_LOGIC_VECTOR(4 downto 0); Rs2_R : out STD_LOGIC_VECTOR(4 downto 0); Subopsw_L : out STD_LOGIC_VECTOR(7 downto 0); Subopsw_R : out STD_LOGIC_VECTOR(7 downto 0); imm_L : out STD_LOGIC_VECTOR(63 downto 0); imm_R : out STD_LOGIC_VECTOR(63 downto 0); valid_L : out STD_LOGIC_VECTOR(0 downto 0); valid_R : out STD_LOGIC_VECTOR(0 downto 0); we_Dcache_L : out STD_LOGIC_VECTOR(0 downto 0); we_Dcache_R : out STD_LOGIC_VECTOR(0 downto 0); we_RF_L : out STD_LOGIC_VECTOR(0 downto 0); we_RF_M_L : out STD_LOGIC_VECTOR(0 downto 0); we_RF_M_R : out STD_LOGIC_VECTOR(0 downto 0); we_RF_R : out STD_LOGIC_VECTOR(0 downto 0); we_pred_L : out STD_LOGIC_VECTOR(0 downto 0); we_pred_R : out STD_LOGIC_VECTOR(0 downto 0); wr_pred_addr1_L : out STD_LOGIC_VECTOR(2 downto 0); wr_pred_addr1_R : out STD_LOGIC_VECTOR(2 downto 0); wr_pred_addr2_L : out STD_LOGIC_VECTOR(2 downto 0); wr_pred_addr2_R : out STD_LOGIC_VECTOR(2 downto 0) ); end component; component ctrl_unit port ( ALU_L : in STD_LOGIC_VECTOR(63 downto 0); ALU_R : in STD_LOGIC_VECTOR(63 downto 0); DFW_Instr_type_L : in STD_LOGIC_VECTOR(8 downto 0); DFW_Instr_type_R : in STD_LOGIC_VECTOR(8 downto 0); DFW_Opcode_L : in STD_LOGIC_VECTOR(5 downto 0); DFW_Opcode_R : in STD_LOGIC_VECTOR(5 downto 0); DFW_PC_L : in STD_LOGIC_VECTOR(31 downto 0); DFW_PC_R : in STD_LOGIC_VECTOR(31 downto 0); DFW_Rd_L : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rd_M_L : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rd_M_R : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rd_R : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rs1_L : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rs1_R : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rs2_L : in STD_LOGIC_VECTOR(4 downto 0); DFW_Rs2_R : in STD_LOGIC_VECTOR(4 downto 0); DFW_Subopsw_L : in STD_LOGIC_VECTOR(7 downto 0); DFW_Subopsw_R : in STD_LOGIC_VECTOR(7 downto 0); DFW_banksel : in STD_LOGIC_VECTOR(3 downto 0); DFW_cache_L : in STD_LOGIC_VECTOR(63 downto 0); DFW_cache_R : in STD_LOGIC_VECTOR(63 downto 0); DFW_data_L : in STD_LOGIC_VECTOR(63 downto 0); DFW_data_R : in STD_LOGIC_VECTOR(63 downto 0); DFW_imm_L : in STD_LOGIC_VECTOR(63 downto 0); DFW_imm_R : in STD_LOGIC_VECTOR(63 downto 0); DFW_pred_L : in STD_LOGIC_VECTOR(2 downto 0); DFW_pred_R : in STD_LOGIC_VECTOR(2 downto 0); DFW_pred_d_L : in STD_LOGIC; DFW_pred_d_R : in STD_LOGIC; DFW_valid_L : in STD_LOGIC_VECTOR(0 downto 0); DFW_valid_R : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_Dcache_L : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_Dcache_R : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_RF_L : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_RF_M_L : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_RF_M_R : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_RF_R : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_pred_L : in STD_LOGIC_VECTOR(0 downto 0); DFW_we_pred_R : in STD_LOGIC_VECTOR(0 downto 0); DFW_wr_pred_addr1_L : in STD_LOGIC_VECTOR(2 downto 0); DFW_wr_pred_addr1_R : in STD_LOGIC_VECTOR(2 downto 0); DFW_wr_pred_addr2_L : in STD_LOGIC_VECTOR(2 downto 0); DFW_wr_pred_addr2_R : in STD_LOGIC_VECTOR(2 downto 0); DRE_Instr_type_L : in STD_LOGIC_VECTOR(8 downto 0); DRE_Instr_type_R : in STD_LOGIC_VECTOR(8 downto 0); DRE_Opcode_L : in STD_LOGIC_VECTOR(5 downto 0); DRE_Opcode_R : in STD_LOGIC_VECTOR(5 downto 0); DRE_PC_L : in STD_LOGIC_VECTOR(31 downto 0); DRE_PC_R : in STD_LOGIC_VECTOR(31 downto 0); DRE_Rd_L : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rd_M_L : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rd_M_R : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rd_R : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rs1_L : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rs1_R : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rs2_L : in STD_LOGIC_VECTOR(4 downto 0); DRE_Rs2_R : in STD_LOGIC_VECTOR(4 downto 0); DRE_Subopsw_L : in STD_LOGIC_VECTOR(7 downto 0); DRE_Subopsw_R : in STD_LOGIC_VECTOR(7 downto 0); DRE_banksel : in STD_LOGIC_VECTOR(3 downto 0); DRE_imm_L : in STD_LOGIC_VECTOR(63 downto 0); DRE_imm_R : in STD_LOGIC_VECTOR(63 downto 0); DRE_pred_L : in STD_LOGIC_VECTOR(2 downto 0); DRE_pred_R : in STD_LOGIC_VECTOR(2 downto 0); DRE_st_L : in STD_LOGIC_VECTOR(63 downto 0); DRE_st_R : in STD_LOGIC_VECTOR(63 downto 0); DRE_unknown : in STD_LOGIC; DRE_valid_L : in STD_LOGIC_VECTOR(0 downto 0); DRE_valid_R : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_Dcache_L : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_Dcache_R : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_RF_L : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_RF_M_L : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_RF_M_R : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_RF_R : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_pred_L : in STD_LOGIC_VECTOR(0 downto 0); DRE_we_pred_R : in STD_LOGIC_VECTOR(0 downto 0); DRE_wr_pred_addr1_L : in STD_LOGIC_VECTOR(2 downto 0); DRE_wr_pred_addr1_R : in STD_LOGIC_VECTOR(2 downto 0); DRE_wr_pred_addr2_L : in STD_LOGIC_VECTOR(2 downto 0); DRE_wr_pred_addr2_R : in STD_LOGIC_VECTOR(2 downto 0); DR_Rs1_L : in STD_LOGIC_VECTOR(63 downto 0); DR_Rs1_R : in STD_LOGIC_VECTOR(63 downto 0); DR_Rs2_L : in STD_LOGIC_VECTOR(63 downto 0); DR_Rs2_R : in STD_LOGIC_VECTOR(63 downto 0); Dcacheout : in STD_LOGIC_VECTOR(63 downto 0); EDF_Instr_type_L : in STD_LOGIC_VECTOR(8 downto 0); EDF_Instr_type_R : in STD_LOGIC_VECTOR(8 downto 0); EDF_Opcode_L : in STD_LOGIC_VECTOR(5 downto 0); EDF_Opcode_R : in STD_LOGIC_VECTOR(5 downto 0); EDF_PC_L : in STD_LOGIC_VECTOR(31 downto 0); EDF_PC_R : in STD_LOGIC_VECTOR(31 downto 0); EDF_Rd_L : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rd_M_L : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rd_M_R : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rd_R : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rs1_L : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rs1_R : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rs2_L : in STD_LOGIC_VECTOR(4 downto 0); EDF_Rs2_R : in STD_LOGIC_VECTOR(4 downto 0); EDF_Subopsw_L : in STD_LOGIC_VECTOR(7 downto 0); EDF_Subopsw_R : in STD_LOGIC_VECTOR(7 downto 0); EDF_banksel : in STD_LOGIC_VECTOR(3 downto 0); EDF_data_L : in STD_LOGIC_VECTOR(63 downto 0); EDF_data_R : in STD_LOGIC_VECTOR(63 downto 0); EDF_imm_L : in STD_LOGIC_VECTOR(63 downto 0); EDF_imm_R : in STD_LOGIC_VECTOR(63 downto 0); EDF_pred_L : in STD_LOGIC_VECTOR(2 downto 0); EDF_pred_R : in STD_LOGIC_VECTOR(2 downto 0); EDF_pred_d_L : in STD_LOGIC; EDF_pred_d_R : in STD_LOGIC; EDF_valid_L : in STD_LOGIC_VECTOR(0 downto 0); EDF_valid_R : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_Dcache_L : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_Dcache_R : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_RF_L : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_RF_M_L : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_RF_M_R : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_RF_R : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_pred_L : in STD_LOGIC_VECTOR(0 downto 0); EDF_we_pred_R : in STD_LOGIC_VECTOR(0 downto 0); EDF_wr_pred_addr1_L : in STD_LOGIC_VECTOR(2 downto 0); EDF_wr_pred_addr1_R : in STD_LOGIC_VECTOR(2 downto 0); EDF_wr_pred_addr2_L : in STD_LOGIC_VECTOR(2 downto 0); EDF_wr_pred_addr2_R : in STD_LOGIC_VECTOR(2 downto 0); IR_Instr_type_L : in STD_LOGIC_VECTOR(8 downto 0); IR_Instr_type_R : in STD_LOGIC_VECTOR(8 downto 0); IR_Opcode_L : in STD_LOGIC_VECTOR(5 downto 0); IR_Opcode_R : in STD_LOGIC_VECTOR(5 downto 0); IR_PC_L : in STD_LOGIC_VECTOR(31 downto 0); IR_PC_R : in STD_LOGIC_VECTOR(31 downto 0); IR_Rd_L : in STD_LOGIC_VECTOR(4 downto 0); IR_Rd_M_L : in STD_LOGIC_VECTOR(4 downto 0); IR_Rd_M_R : in STD_LOGIC_VECTOR(4 downto 0); IR_Rd_R : in STD_LOGIC_VECTOR(4 downto 0); IR_Rs1_L : in STD_LOGIC_VECTOR(4 downto 0); IR_Rs1_R : in STD_LOGIC_VECTOR(4 downto 0); IR_Rs2_L : in STD_LOGIC_VECTOR(4 downto 0); IR_Rs2_R : in STD_LOGIC_VECTOR(4 downto 0); IR_Subopsw_L : in STD_LOGIC_VECTOR(7 downto 0); IR_Subopsw_R : in STD_LOGIC_VECTOR(7 downto 0); IR_banksel : in STD_LOGIC_VECTOR(3 downto 0); IR_imm_L : in STD_LOGIC_VECTOR(63 downto 0); IR_imm_R : in STD_LOGIC_VECTOR(63 downto 0); IR_pred_L : in STD_LOGIC_VECTOR(2 downto 0); IR_pred_R : in STD_LOGIC_VECTOR(2 downto 0); IR_pred_d_L : in STD_LOGIC; IR_pred_d_R : in STD_LOGIC; IR_pred_imm4_L : in STD_LOGIC_VECTOR(3 downto 0); IR_pred_imm4_R : in STD_LOGIC_VECTOR(3 downto 0); IR_pred_imm8_L : in STD_LOGIC_VECTOR(7 downto 0); IR_pred_imm8_R : in STD_LOGIC_VECTOR(7 downto 0); IR_we_Dcache_L : in STD_LOGIC_VECTOR(0 downto 0); IR_we_Dcache_R : in STD_LOGIC_VECTOR(0 downto 0); IR_we_RF_L : in STD_LOGIC_VECTOR(0 downto 0); IR_we_RF_M_L : in STD_LOGIC_VECTOR(0 downto 0); IR_we_RF_M_R : in STD_LOGIC_VECTOR(0 downto 0); IR_we_RF_R : in STD_LOGIC_VECTOR(0 downto 0); IR_we_pred_L : in STD_LOGIC_VECTOR(0 downto 0); IR_we_pred_R : in STD_LOGIC_VECTOR(0 downto 0); IR_wr_pred_addr1_L : in STD_LOGIC_VECTOR(2 downto 0); IR_wr_pred_addr1_R : in STD_LOGIC_VECTOR(2 downto 0); IR_wr_pred_addr2_L : in STD_LOGIC_VECTOR(2 downto 0); IR_wr_pred_addr2_R : in STD_LOGIC_VECTOR(2 downto 0); MULDFW_L : in STD_LOGIC_VECTOR(5 downto 0); MULDFW_R : in STD_LOGIC_VECTOR(5 downto 0); MULEDF_L : in STD_LOGIC_VECTOR(5 downto 0); MULEDF_R : in STD_LOGIC_VECTOR(5 downto 0); MUL_L : in STD_LOGIC_VECTOR(63 downto 0); MUL_R : in STD_LOGIC_VECTOR(63 downto 0); SHF_L : in STD_LOGIC_VECTOR(63 downto 0); SHF_R : in STD_LOGIC_VECTOR(63 downto 0); reset : in STD_LOGIC; ALUoutL : out STD_LOGIC_VECTOR(63 downto 0); ALUoutR : out STD_LOGIC_VECTOR(63 downto 0); CMPresuL : out STD_LOGIC; CMPresuR : out STD_LOGIC; DRMUX1_L : out STD_LOGIC_VECTOR(63 downto 0); DRMUX1_R : out STD_LOGIC_VECTOR(63 downto 0); DRMUX2_L : out STD_LOGIC_VECTOR(63 downto 0); DRMUX2_R : out STD_LOGIC_VECTOR(63 downto 0); DR_unknown : out STD_LOGIC; DR_valid_L : out STD_LOGIC; DR_valid_R : out STD_LOGIC; Dcache_we : out STD_LOGIC; E_st_addr : out STD_LOGIC_VECTOR(31 downto 0); E_st_data : out STD_LOGIC_VECTOR(63 downto 0); E_valid_R : out STD_LOGIC; JMP_disp : out STD_LOGIC_VECTOR(31 downto 0); JMPvalidL : out STD_LOGIC; JMPvalidR : out STD_LOGIC; MULpipe_L : out STD_LOGIC_VECTOR(5 downto 0); MULpipe_R : out STD_LOGIC_VECTOR(5 downto 0); PCstall : out STD_LOGIC; RF_Rd_L : out STD_LOGIC_VECTOR(4 downto 0); RF_Rd_M : out STD_LOGIC_VECTOR(4 downto 0); RF_Rd_R : out STD_LOGIC_VECTOR(4 downto 0); RF_data_L : out STD_LOGIC_VECTOR(63 downto 0); RF_data_M : out STD_LOGIC_VECTOR(63 downto 0); RF_data_R : out STD_LOGIC_VECTOR(63 downto 0); RF_we_L : out STD_LOGIC; RF_we_M : out STD_LOGIC; RF_we_R : out STD_LOGIC; chpr_imm4 : out STD_LOGIC_VECTOR(3 downto 0); chpr_valid : out STD_LOGIC; pred_imm8 : out STD_LOGIC_VECTOR(7 downto 0); pred_we8b : out STD_LOGIC; pred_we_L : out STD_LOGIC; pred_we_R : out STD_LOGIC; stallL : out STD_LOGIC; stallR : out STD_LOGIC ); end component; component dcaceh_tmp port ( Raddr : in STD_LOGIC_VECTOR(31 downto 0); Waddr : in STD_LOGIC_VECTOR(31 downto 0); Wdata : in STD_LOGIC_VECTOR(63 downto 0); we : in STD_LOGIC; Dcacheout : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component dffr_1bit port ( CK_L : in STD_LOGIC; D : in STD_LOGIC; RS_L : in STD_LOGIC; Q : out STD_LOGIC ); end component; component dreg_dfw generic( Td_ck_out : TIME := 0 ns ); port ( ALUout_L : in STD_LOGIC_VECTOR(63 downto 0); ALUout_R : in STD_LOGIC_VECTOR(63 downto 0); cache_data : in STD_LOGIC_VECTOR(63 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; Q_cachedata : out STD_LOGIC_VECTOR(63 downto 0); data_L : out STD_LOGIC_VECTOR(63 downto 0); data_R : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component Dreg_DRE generic( Td_ck_out : TIME ); port ( D_st_L : in STD_LOGIC_VECTOR(63 downto 0); D_st_R : in STD_LOGIC_VECTOR(63 downto 0); clk : in STD_LOGIC; op1_L : in STD_LOGIC_VECTOR(63 downto 0); op1_R : in STD_LOGIC_VECTOR(63 downto 0); op2_L : in STD_LOGIC_VECTOR(63 downto 0); op2_R : in STD_LOGIC_VECTOR(63 downto 0); reset : in STD_LOGIC; Q_op1_L : out STD_LOGIC_VECTOR(63 downto 0); Q_op1_R : out STD_LOGIC_VECTOR(63 downto 0); Q_op2_L : out STD_LOGIC_VECTOR(63 downto 0); Q_op2_R : out STD_LOGIC_VECTOR(63 downto 0); Q_st_L : out STD_LOGIC_VECTOR(63 downto 0); Q_st_R : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component Dreg_EDF generic( Td_ck_out : TIME ); port ( ALU_L : in STD_LOGIC_VECTOR(63 downto 0); ALU_R : in STD_LOGIC_VECTOR(63 downto 0); addr_dcache : in STD_LOGIC_VECTOR(31 downto 0); clk : in STD_LOGIC; data_dcache : in STD_LOGIC_VECTOR(63 downto 0); reset : in STD_LOGIC; ALUout_L : out STD_LOGIC_VECTOR(63 downto 0); ALUout_R : out STD_LOGIC_VECTOR(63 downto 0); Q_addr : out STD_LOGIC_VECTOR(31 downto 0); Q_data : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component DREG_IFDR port ( CLK : in STD_LOGIC; I_IR_L : in STD_LOGIC_VECTOR(31 downto 0); I_IR_L_after : in STD_LOGIC_VECTOR(31 downto 0); I_IR_R : in STD_LOGIC_VECTOR(31 downto 0); I_IR_R_after : in STD_LOGIC_VECTOR(31 downto 0); I_PC_L : in STD_LOGIC_VECTOR(31 downto 0); I_PC_R : in STD_LOGIC_VECTOR(31 downto 0); reset : in STD_LOGIC; stall0 : in STD_LOGIC; stall1 : in STD_LOGIC; IR_L : out STD_LOGIC_VECTOR(31 downto 0); IR_R : out STD_LOGIC_VECTOR(31 downto 0); PC_L : out STD_LOGIC_VECTOR(31 downto 0); PC_R : out STD_LOGIC_VECTOR(31 downto 0) ); end component; component Inst_decoder generic( Tac : TIME := 0 ns; origin_x : REAL := 0.000000; origin_y : REAL := 0.000000; tag : STRING := "" ); port ( IR_L : in STD_LOGIC_VECTOR(31 downto 0); IR_R : in STD_LOGIC_VECTOR(31 downto 0); Instr_type_L : out STD_LOGIC_VECTOR(8 downto 0); Instr_type_R : out STD_LOGIC_VECTOR(8 downto 0); Opcode_L : out STD_LOGIC_VECTOR(5 downto 0); Opcode_R : out STD_LOGIC_VECTOR(5 downto 0); Rd_L : out STD_LOGIC_VECTOR(4 downto 0); Rd_M_L : out STD_LOGIC_VECTOR(4 downto 0); Rd_M_R : out STD_LOGIC_VECTOR(4 downto 0); Rd_R : out STD_LOGIC_VECTOR(4 downto 0); Rs1_L : out STD_LOGIC_VECTOR(4 downto 0); Rs1_R : out STD_LOGIC_VECTOR(4 downto 0); Rs2_L : out STD_LOGIC_VECTOR(4 downto 0); Rs2_R : out STD_LOGIC_VECTOR(4 downto 0); Subopsw_L : out STD_LOGIC_VECTOR(7 downto 0); Subopsw_R : out STD_LOGIC_VECTOR(7 downto 0); imm_L : out STD_LOGIC_VECTOR(63 downto 0); imm_R : out STD_LOGIC_VECTOR(63 downto 0); pred_L : out STD_LOGIC_VECTOR(2 downto 0); pred_R : out STD_LOGIC_VECTOR(2 downto 0); pred_imm4_L : out STD_LOGIC_VECTOR(3 downto 0); pred_imm4_R : out STD_LOGIC_VECTOR(3 downto 0); pred_imm8_L : out STD_LOGIC_VECTOR(7 downto 0); pred_imm8_R : out STD_LOGIC_VECTOR(7 downto 0); we_Dcache_L : out STD_LOGIC_VECTOR(0 downto 0); we_Dcache_R : out STD_LOGIC_VECTOR(0 downto 0); we_RF_L : out STD_LOGIC_VECTOR(0 downto 0); we_RF_M_L : out STD_LOGIC_VECTOR(0 downto 0); we_RF_M_R : out STD_LOGIC_VECTOR(0 downto 0); we_RF_R : out STD_LOGIC_VECTOR(0 downto 0); we_pred_L : out STD_LOGIC_VECTOR(0 downto 0); we_pred_R : out STD_LOGIC_VECTOR(0 downto 0); wr_pred_addr1_L : out STD_LOGIC_VECTOR(2 downto 0); wr_pred_addr1_R : out STD_LOGIC_VECTOR(2 downto 0); wr_pred_addr2_L : out STD_LOGIC_VECTOR(2 downto 0); wr_pred_addr2_R : out STD_LOGIC_VECTOR(2 downto 0) ); end component; component I_Cache generic( prop : TIME := 26 ns ); port ( address : in STD_LOGIC_VECTOR(31 downto 0); oen : in STD_LOGIC; instr1 : out STD_LOGIC_VECTOR(31 downto 0); instr2 : out STD_LOGIC_VECTOR(31 downto 0); instr3 : out STD_LOGIC_VECTOR(31 downto 0); instr4 : out STD_LOGIC_VECTOR(31 downto 0) ); end component; component mul port ( Op1 : in STD_LOGIC_VECTOR(63 downto 0); Op2 : in STD_LOGIC_VECTOR(63 downto 0); Opcode : in STD_LOGIC_VECTOR(5 downto 0); Subop : in STD_LOGIC_VECTOR(7 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; MulOut : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component mulpipe port ( I_MULL : in STD_LOGIC_VECTOR(5 downto 0); I_MULR : in STD_LOGIC_VECTOR(5 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; MULL : out STD_LOGIC_VECTOR(5 downto 0); MULR : out STD_LOGIC_VECTOR(5 downto 0) ); end component; component my_inv port ( I : in STD_LOGIC; O : out STD_LOGIC ); end component; component PC_gen generic( Tac : TIME := 1 ns; origin_x : REAL := 0.000000; origin_y : REAL := 0.000000; tag : STRING := "" ); port ( I_PC : in STD_LOGIC_VECTOR(31 downto 0); I_PC_4 : in STD_LOGIC_VECTOR(31 downto 0); JMPvalidL : in STD_LOGIC; JMPvalidR : in STD_LOGIC; clk : in STD_LOGIC; disp : in STD_LOGIC_VECTOR(31 downto 0); reset : in STD_LOGIC; stallL : in STD_LOGIC; stallR : in STD_LOGIC; PC_4out : out STD_LOGIC_VECTOR(31 downto 0); PCout : out STD_LOGIC_VECTOR(31 downto 0) ); end component; component pred_IFDR port ( chpr_valid : in STD_LOGIC; clk : in STD_LOGIC; imm4 : in STD_LOGIC_VECTOR(3 downto 0); reset : in STD_LOGIC; bank_sel : out STD_LOGIC_VECTOR(3 downto 0) ); end component; component pred_pipereg port ( I_8_valid : in STD_LOGIC; I_Data_L : in STD_LOGIC; I_bank : in STD_LOGIC_VECTOR(3 downto 0); I_data_R : in STD_LOGIC; I_imm8 : in STD_LOGIC_VECTOR(7 downto 0); I_pred_L : in STD_LOGIC_VECTOR(2 downto 0); I_pred_R : in STD_LOGIC_VECTOR(2 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; Data_L : out STD_LOGIC; Data_R : out STD_LOGIC; O_8_valid : out STD_LOGIC; bank : out STD_LOGIC_VECTOR(3 downto 0); imm8 : out STD_LOGIC_VECTOR(7 downto 0); pred_L : out STD_LOGIC_VECTOR(2 downto 0); pred_R : out STD_LOGIC_VECTOR(2 downto 0) ); end component; component pred_reg_v2 port ( imm8 : in STD_LOGIC_VECTOR(7 downto 0); rd_addr_L : in STD_LOGIC_VECTOR(2 downto 0); rd_addr_R : in STD_LOGIC_VECTOR(2 downto 0); rd_banksel : in STD_LOGIC_VECTOR(3 downto 0); reset : in STD_LOGIC; we_8b : in STD_LOGIC; we_L : in STD_LOGIC; we_R : in STD_LOGIC; wr_addr1_L : in STD_LOGIC_VECTOR(2 downto 0); wr_addr1_R : in STD_LOGIC_VECTOR(2 downto 0); wr_addr2_L : in STD_LOGIC_VECTOR(2 downto 0); wr_addr2_R : in STD_LOGIC_VECTOR(2 downto 0); wr_banksel : in STD_LOGIC_VECTOR(3 downto 0); wr_d1_L : in STD_LOGIC; wr_d1_R : in STD_LOGIC; wr_d2_L : in STD_LOGIC; wr_d2_R : in STD_LOGIC; out_L : out STD_LOGIC; out_R : out STD_LOGIC ); end component; component regfile generic( Tac : TIME := 1 ns; origin_x : REAL := 0.000000; origin_y : REAL := 0.000000; tag : STRING := "" ); port ( rd_a_L1 : in STD_LOGIC_VECTOR(4 downto 0); rd_a_L2 : in STD_LOGIC_VECTOR(4 downto 0); rd_a_R1 : in STD_LOGIC_VECTOR(4 downto 0); rd_a_R2 : in STD_LOGIC_VECTOR(4 downto 0); we_L : in STD_LOGIC; we_M : in STD_LOGIC; we_R : in STD_LOGIC; wr_a_L : in STD_LOGIC_VECTOR(4 downto 0); wr_a_M : in STD_LOGIC_VECTOR(4 downto 0); wr_a_R : in STD_LOGIC_VECTOR(4 downto 0); wr_d_L : in STD_LOGIC_VECTOR(63 downto 0); wr_d_M : in STD_LOGIC_VECTOR(63 downto 0); wr_d_R : in STD_LOGIC_VECTOR(63 downto 0); rd_q_L1 : out STD_LOGIC_VECTOR(63 downto 0); rd_q_L2 : out STD_LOGIC_VECTOR(63 downto 0); rd_q_R1 : out STD_LOGIC_VECTOR(63 downto 0); rd_q_R2 : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component sp port ( CLOCK : in STD_LOGIC; Opcode : in STD_LOGIC_VECTOR(5 downto 0); Rs1 : in STD_LOGIC_VECTOR(63 downto 0); Rs2 : in STD_LOGIC_VECTOR(63 downto 0); Subop : in STD_LOGIC_VECTOR(12 downto 0); Data : out STD_LOGIC_VECTOR(63 downto 0) ); end component; component Subop13 port ( Inst_L : in STD_LOGIC_VECTOR(31 downto 0); Inst_R : in STD_LOGIC_VECTOR(31 downto 0); subop_L : out STD_LOGIC_VECTOR(12 downto 0); subop_R : out STD_LOGIC_VECTOR(12 downto 0) ); end component; ---- Constants ----- constant DANGLING_INPUT_CONSTANT : STD_LOGIC := 'Z'; constant VCC_CONSTANT : STD_LOGIC := '1'; constant GND_CONSTANT : STD_LOGIC := '0'; ---- Signal declarations used on the diagram ---- signal a : std_logic_vector (63 downto 0); signal b : std_logic_vector (31 downto 0); signal BUS22962 : STD_LOGIC_VECTOR (31 downto 0); signal BUS29446 : STD_LOGIC_VECTOR (3 downto 0); signal BUS29526 : STD_LOGIC_VECTOR (7 downto 0); signal BUS29623 : STD_LOGIC_VECTOR (2 downto 0); signal BUS29629 : STD_LOGIC_VECTOR (2 downto 0); signal BUS29641 : STD_LOGIC_VECTOR (2 downto 0); signal BUS29809 : STD_LOGIC_VECTOR (2 downto 0); signal BUS31888 : STD_LOGIC_VECTOR (31 downto 0); signal BUS32179 : STD_LOGIC_VECTOR (63 downto 0); signal BUS32185 : STD_LOGIC_VECTOR (31 downto 0); signal BUS4081 : STD_LOGIC_VECTOR (0 downto 0); signal BUS4097 : STD_LOGIC_VECTOR (0 downto 0); signal BUS4143 : STD_LOGIC_VECTOR (0 downto 0); signal BUS4155 : STD_LOGIC_VECTOR (4 downto 0); signal BUS4171 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62147 : STD_LOGIC_VECTOR (8 downto 0); signal BUS62194 : STD_LOGIC_VECTOR (8 downto 0); signal BUS62201 : STD_LOGIC_VECTOR (5 downto 0); signal BUS62208 : STD_LOGIC_VECTOR (5 downto 0); signal BUS62222 : STD_LOGIC_VECTOR (31 downto 0); signal BUS62229 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62236 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62243 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62250 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62257 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62264 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62271 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62278 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62285 : STD_LOGIC_VECTOR (7 downto 0); signal BUS62292 : STD_LOGIC_VECTOR (7 downto 0); signal BUS62303 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62310 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62339 : STD_LOGIC_VECTOR (3 downto 0); signal BUS62382 : STD_LOGIC_VECTOR (3 downto 0); signal BUS62385 : STD_LOGIC_VECTOR (7 downto 0); signal BUS62393 : STD_LOGIC_VECTOR (7 downto 0); signal BUS62405 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62412 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62423 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62434 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62445 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62456 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62467 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62478 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62489 : STD_LOGIC_VECTOR (2 downto 0); signal BUS62500 : STD_LOGIC_VECTOR (2 downto 0); signal BUS62511 : STD_LOGIC_VECTOR (2 downto 0); signal BUS62522 : STD_LOGIC_VECTOR (2 downto 0); signal BUS62525 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62695 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62707 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62778 : STD_LOGIC_VECTOR (8 downto 0); signal BUS62785 : STD_LOGIC_VECTOR (8 downto 0); signal BUS62806 : STD_LOGIC_VECTOR (31 downto 0); signal BUS62813 : STD_LOGIC_VECTOR (31 downto 0); signal BUS62820 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62827 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62834 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62841 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62848 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62855 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62864 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62874 : STD_LOGIC_VECTOR (4 downto 0); signal BUS62902 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62916 : STD_LOGIC_VECTOR (2 downto 0); signal BUS62923 : STD_LOGIC_VECTOR (2 downto 0); signal BUS62926 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62932 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62948 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62955 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62962 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62969 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62976 : STD_LOGIC_VECTOR (63 downto 0); signal BUS62986 : STD_LOGIC_VECTOR (0 downto 0); signal BUS62996 : STD_LOGIC_VECTOR (0 downto 0); signal BUS63006 : STD_LOGIC_VECTOR (0 downto 0); signal BUS63016 : STD_LOGIC_VECTOR (0 downto 0); signal BUS63039 : STD_LOGIC_VECTOR (0 downto 0); signal BUS63050 : STD_LOGIC_VECTOR (0 downto 0); signal BUS63061 : STD_LOGIC_VECTOR (2 downto 0); signal BUS63072 : STD_LOGIC_VECTOR (2 downto 0); signal BUS63083 : STD_LOGIC_VECTOR (2 downto 0); signal BUS63094 : STD_LOGIC_VECTOR (2 downto 0); signal BUS63105 : STD_LOGIC_VECTOR (8 downto 0); signal BUS63133 : STD_LOGIC_VECTOR (8 downto 0); signal BUS63145 : STD_LOGIC_VECTOR (5 downto 0); signal BUS63156 : STD_LOGIC_VECTOR (5 downto 0); signal BUS63167 : STD_LOGIC_VECTOR (31 downto 0); signal BUS63178 : STD_LOGIC_VECTOR (31 downto 0); signal BUS63189 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63200 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63211 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63222 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63233 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63240 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63247 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63254 : STD_LOGIC_VECTOR (4 downto 0); signal BUS63261 : STD_LOGIC_VECTOR (7 downto 0); signal BUS63268 : STD_LOGIC_VECTOR (7 downto 0); signal BUS63281 : STD_LOGIC_VECTOR (63 downto 0); signal BUS63288 : STD_LOGIC_VECTOR (63 downto 0); signal BUS63295 : STD_LOGIC_VECTOR (63 downto 0); signal BUS63302 : STD_LOGIC_VECTOR (63 downto 0); signal BUS63309 : STD_LOGIC_VECTOR (2 downto 0); signal BUS63316 : STD_LOGIC_VECTOR (2 downto 0); signal BUS64038 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64045 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64052 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64059 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64066 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64075 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64085 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64095 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64323 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64333 : STD_LOGIC_VECTOR (0 downto 0); signal BUS64343 : STD_LOGIC_VECTOR (2 downto 0); signal BUS64353 : STD_LOGIC_VECTOR (2 downto 0); signal BUS64363 : STD_LOGIC_VECTOR (2 downto 0); signal BUS64371 : STD_LOGIC_VECTOR (2 downto 0); signal BUS64380 : STD_LOGIC_VECTOR (5 downto 0); signal BUS64428 : STD_LOGIC_VECTOR (5 downto 0); signal BUS64505 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64517 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64708 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64749 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64771 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64804 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64818 : STD_LOGIC_VECTOR (63 downto 0); signal BUS64832 : STD_LOGIC_VECTOR (8 downto 0); signal BUS64842 : STD_LOGIC_VECTOR (8 downto 0); signal BUS64852 : STD_LOGIC_VECTOR (5 downto 0); signal BUS64862 : STD_LOGIC_VECTOR (5 downto 0); signal BUS64872 : STD_LOGIC_VECTOR (31 downto 0); signal BUS64882 : STD_LOGIC_VECTOR (31 downto 0); signal BUS69361 : STD_LOGIC_VECTOR (4 downto 0); signal BUS69379 : STD_LOGIC_VECTOR (4 downto 0); signal BUS69389 : STD_LOGIC_VECTOR (4 downto 0); signal BUS69399 : STD_LOGIC_VECTOR (4 downto 0); signal BUS69409 : STD_LOGIC_VECTOR (4 downto 0); signal BUS69419 : STD_LOGIC_VECTOR (7 downto 0); signal BUS69429 : STD_LOGIC_VECTOR (7 downto 0); signal BUS69547 : STD_LOGIC_VECTOR (63 downto 0); signal BUS69553 : STD_LOGIC_VECTOR (63 downto 0); signal BUS69559 : STD_LOGIC_VECTOR (2 downto 0); signal BUS69565 : STD_LOGIC_VECTOR (2 downto 0); signal BUS69765 : STD_LOGIC_VECTOR (0 downto 0); signal BUS69771 : STD_LOGIC_VECTOR (0 downto 0); signal BUS69777 : STD_LOGIC_VECTOR (0 downto 0); signal BUS69783 : STD_LOGIC_VECTOR (0 downto 0); signal BUS69797 : STD_LOGIC_VECTOR (0 downto 0); signal BUS69839 : STD_LOGIC_VECTOR (5 downto 0); signal BUS69845 : STD_LOGIC_VECTOR (5 downto 0); signal BUS69879 : STD_LOGIC_VECTOR (63 downto 0); signal BUS69887 : STD_LOGIC_VECTOR (63 downto 0); signal BUS70788 : STD_LOGIC_VECTOR (63 downto 0); signal BUS70800 : STD_LOGIC_VECTOR (63 downto 0); signal BUS70806 : STD_LOGIC_VECTOR (63 downto 0); signal BUS70812 : STD_LOGIC_VECTOR (63 downto 0); signal BUS70851 : STD_LOGIC_VECTOR (31 downto 0); signal BUS70857 : STD_LOGIC_VECTOR (63 downto 0); signal BUS70910 : STD_LOGIC_VECTOR (31 downto 0); signal BUS70975 : STD_LOGIC_VECTOR (5 downto 0); signal BUS70981 : STD_LOGIC_VECTOR (5 downto 0); signal BUS71069 : STD_LOGIC_VECTOR (4 downto 0); signal BUS71088 : STD_LOGIC_VECTOR (4 downto 0); signal BUS71098 : STD_LOGIC_VECTOR (4 downto 0); signal BUS71107 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71108 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71110 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71114 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71124 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71134 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71174 : STD_LOGIC_VECTOR (3 downto 0); signal BUS71226 : STD_LOGIC_VECTOR (7 downto 0); signal BUS71246 : STD_LOGIC_VECTOR (0 downto 0); signal BUS71248 : STD_LOGIC_VECTOR (0 downto 0); signal BUS71303 : STD_LOGIC_VECTOR (3 downto 0); signal BUS71317 : STD_LOGIC_VECTOR (7 downto 0); signal BUS71452 : STD_LOGIC_VECTOR (3 downto 0); signal BUS71490 : STD_LOGIC_VECTOR (3 downto 0); signal BUS71493 : STD_LOGIC_VECTOR (7 downto 0); signal BUS71910 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71933 : STD_LOGIC_VECTOR (63 downto 0); signal BUS71955 : STD_LOGIC_VECTOR (63 downto 0); signal BUS72010 : STD_LOGIC_VECTOR (63 downto 0); signal BUS72341 : STD_LOGIC_VECTOR (7 downto 0); signal BUS72370 : STD_LOGIC_VECTOR (7 downto 0); signal BUS72394 : STD_LOGIC_VECTOR (5 downto 0); signal BUS72496 : STD_LOGIC_VECTOR (2 downto 0); signal BUS72497 : STD_LOGIC_VECTOR (31 downto 0); signal BUS72507 : STD_LOGIC_VECTOR (2 downto 0); signal BUS72955 : STD_LOGIC_VECTOR (5 downto 0); signal BUS72956 : STD_LOGIC_VECTOR (63 downto 0); signal BUS73041 : STD_LOGIC_VECTOR (31 downto 0); signal BUS73070 : STD_LOGIC_VECTOR (31 downto 0); signal BUS73275 : STD_LOGIC_VECTOR (31 downto 0); signal BUS73281 : STD_LOGIC_VECTOR (31 downto 0); signal BUS73291 : STD_LOGIC_VECTOR (12 downto 0); signal BUS73301 : STD_LOGIC_VECTOR (12 downto 0); signal BUS90027 : STD_LOGIC_VECTOR (4 downto 0); signal BUS90866 : STD_LOGIC_VECTOR (31 downto 0); signal BUS90894 : STD_LOGIC_VECTOR (31 downto 0); signal NET29292 : STD_LOGIC; signal NET29295 : STD_LOGIC; signal NET29405 : STD_LOGIC; signal NET29415 : STD_LOGIC; signal NET29486 : STD_LOGIC; signal NET62327 : STD_LOGIC; signal NET62333 : STD_LOGIC; signal NET62938 : STD_LOGIC; signal NET63331 : STD_LOGIC; signal NET63337 : STD_LOGIC; signal NET70776 : STD_LOGIC; signal NET70782 : STD_LOGIC; signal NET70818 : STD_LOGIC; signal NET70824 : STD_LOGIC; signal NET70830 : STD_LOGIC; signal NET70836 : STD_LOGIC; signal NET70900 : STD_LOGIC; signal NET70918 : STD_LOGIC; signal NET71144 : STD_LOGIC; signal NET71154 : STD_LOGIC; signal NET71164 : STD_LOGIC; signal NET71184 : STD_LOGIC; signal NET71232 : STD_LOGIC; signal NET71257 : STD_LOGIC; signal NET71267 : STD_LOGIC; signal NET71277 : STD_LOGIC; signal NET71311 : STD_LOGIC; signal NET71470 : STD_LOGIC; signal NET81503 : STD_LOGIC; signal NET86513 : STD_LOGIC; ---- Power signals declarations ----- signal VCC : STD_LOGIC; ---- Ground signals declarations ----- signal GND : STD_LOGIC; ---- Declaration for Dangling input ---- signal Dangling_Input_Signal : STD_LOGIC; begin ---- Component instantiations ---- DFW : Ctrl_reg port map( I_Instr_type_L => BUS63105, I_Instr_type_R => BUS63133, I_Opcode_L => BUS63145, I_Opcode_R => BUS63156, I_PC_L => BUS63178, I_PC_R => BUS63167, I_Rd_L => BUS63189, I_Rd_M_L => BUS63200, I_Rd_M_R => BUS63211, I_Rd_R => BUS63222, I_Rs1_L => BUS63233, I_Rs1_R => BUS63240, I_Rs2_L => BUS63247, I_Rs2_R => BUS63254, I_Subopsw_L => BUS63261, I_Subopsw_R => BUS63268, I_imm_L => BUS63295, I_imm_R => BUS63302, I_valid_L => BUS64038, I_valid_R => BUS64045, I_we_Dcache_L => BUS64052, I_we_Dcache_R => BUS64059, I_we_RF_L => BUS64066, I_we_RF_M_L => BUS64075, I_we_RF_M_R => BUS64085, I_we_RF_R => BUS64095, I_we_pred_L => BUS64323, I_we_pred_R => BUS64333, I_wr_pred_addr1_L => BUS64343, I_wr_pred_addr1_R => BUS64353, I_wr_pred_addr2_L => BUS64363, I_wr_pred_addr2_R => BUS64371, Instr_type_L => BUS64832, Instr_type_R => BUS64842, Opcode_L => BUS64852, Opcode_R => BUS64862, PC_L => BUS64872, PC_R => BUS64882, Rd_L => BUS90027, Rd_M_L => BUS4171, Rd_M_R => BUS69361, Rd_R => BUS4155, Rs1_L => BUS69379, Rs1_R => BUS69389, Rs2_L => BUS69399, Rs2_R => BUS69409, Subopsw_L => BUS69419, Subopsw_R => BUS69429, clk => clk, imm_L => BUS69547, imm_R => BUS69553, reset => reset, valid_L => BUS69765, valid_R => BUS69771, we_Dcache_L => BUS69777, we_Dcache_R => BUS69783, we_RF_L => BUS4097, we_RF_M_L => BUS4143, we_RF_M_R => BUS69797, we_RF_R => BUS4081, we_pred_L => BUS71246, we_pred_R => BUS71248, wr_pred_addr1_L => BUS29641, wr_pred_addr1_R => BUS29809, wr_pred_addr2_L => BUS29629, wr_pred_addr2_R => BUS29623 ); DF_W : dreg_dfw port map( ALUout_L => BUS63281, ALUout_R => BUS63288, Q_cachedata => BUS71108, cache_data => BUS64771, clk => clk, data_L => BUS71110, data_R => BUS71107, reset => reset ); DRE : Ctrl_reg port map( I_Instr_type_L => BUS62147, I_Instr_type_R => BUS62194, I_Opcode_L => BUS62201, I_Opcode_R => BUS62208, I_PC_L => BUS72497, I_PC_R => BUS62222, I_Rd_L => BUS62229, I_Rd_M_L => BUS62236, I_Rd_M_R => BUS62243, I_Rd_R => BUS62250, I_Rs1_L => BUS62257, I_Rs1_R => BUS62264, I_Rs2_L => BUS62271, I_Rs2_R => BUS62278, I_Subopsw_L => BUS62285, I_Subopsw_R => BUS62292, I_valid_L(0) => NET70824, I_valid_R(0) => NET70830, I_imm_L => BUS62303, I_imm_R => BUS62310, I_we_Dcache_L => BUS62405, I_we_Dcache_R => BUS62412, I_we_RF_L => BUS62423, I_we_RF_M_L => BUS62434, I_we_RF_M_R => BUS62445, I_we_RF_R => BUS62456, I_we_pred_L => BUS62467, I_we_pred_R => BUS62478, I_wr_pred_addr1_L => BUS62489, I_wr_pred_addr1_R => BUS62500, I_wr_pred_addr2_L => BUS62511, I_wr_pred_addr2_R => BUS62522, Instr_type_L => BUS62778, Instr_type_R => BUS62785, Opcode_L => BUS72955, Opcode_R => BUS72394, PC_L => BUS62806, PC_R => BUS62813, Rd_L => BUS62820, Rd_M_L => BUS62827, Rd_M_R => BUS62834, Rd_R => BUS62841, Rs1_L => BUS62848, Rs1_R => BUS62855, Rs2_L => BUS62864, Rs2_R => BUS62874, Subopsw_L => BUS72341, Subopsw_R => BUS72370, clk => clk, imm_L => BUS62902, imm_R => BUS62976, reset => reset, valid_L => BUS62948, valid_R => BUS62955, we_Dcache_L => BUS62962, we_Dcache_R => BUS62969, we_RF_L => BUS62986, we_RF_M_L => BUS62996, we_RF_M_R => BUS63006, we_RF_R => BUS63016, we_pred_L => BUS63039, we_pred_R => BUS63050, wr_pred_addr1_L => BUS63061, wr_pred_addr1_R => BUS63072, wr_pred_addr2_L => BUS63083, wr_pred_addr2_R => BUS63094 ); DRE_unknown : dffr_1bit port map( CK_L => clk, D => NET70818, Q => NET62938, RS_L => reset ); DR_E : Dreg_DRE generic map ( Td_ck_out => 0 ns ) port map( D_st_L => BUS62707, D_st_R => BUS72956, Q_op1_L => BUS71910, Q_op1_R => BUS71955, Q_op2_L => BUS71933, Q_op2_R => BUS72010, Q_st_L => BUS62926, Q_st_R => BUS62932, clk => clk, op1_L => BUS70788, op1_R => BUS70800, op2_L => BUS70806, op2_R => BUS70812, reset => reset ); EDF : Ctrl_reg port map( I_Instr_type_L => BUS62778, I_Instr_type_R => BUS62785, I_Opcode_L => BUS72955, I_Opcode_R => BUS72394, I_PC_L => BUS62813, I_PC_R => BUS62806, I_Rd_L => BUS62820, I_Rd_M_L => BUS62827, I_Rd_M_R => BUS62834, I_Rd_R => BUS62841, I_Rs1_L => BUS62848, I_Rs1_R => BUS62855, I_Rs2_L => BUS62864, I_Rs2_R => BUS62874, I_Subopsw_L => BUS72341, I_Subopsw_R => BUS72370, I_valid_R(0) => NET70900, I_imm_L => BUS62902, I_imm_R => BUS62976, I_valid_L => BUS62948, I_we_Dcache_L => BUS62962, I_we_Dcache_R => BUS62969, I_we_RF_L => BUS62986, I_we_RF_M_L => BUS62996, I_we_RF_M_R => BUS63006, I_we_RF_R => BUS63016, I_we_pred_L => BUS63039, I_we_pred_R => BUS63050, I_wr_pred_addr1_L => BUS63061, I_wr_pred_addr1_R => BUS63072, I_wr_pred_addr2_L => BUS63083, I_wr_pred_addr2_R => BUS63094, Instr_type_L => BUS63105, Instr_type_R => BUS63133, Opcode_L => BUS63145, Opcode_R => BUS63156, PC_L => BUS63167, PC_R => BUS63178, Rd_L => BUS63189, Rd_M_L => BUS63200, Rd_M_R => BUS63211, Rd_R => BUS63222, Rs1_L => BUS63233, Rs1_R => BUS63240, Rs2_L => BUS63247, Rs2_R => BUS63254, Subopsw_L => BUS63261, Subopsw_R => BUS63268, clk => clk, imm_L => BUS63295, imm_R => BUS63302, reset => reset, valid_L => BUS64038, valid_R => BUS64045, we_Dcache_L => BUS64052, we_Dcache_R => BUS64059, we_RF_L => BUS64066, we_RF_M_L => BUS64075, we_RF_M_R => BUS64085, we_RF_R => BUS64095, we_pred_L => BUS64323, we_pred_R => BUS64333, wr_pred_addr1_L => BUS64343, wr_pred_addr1_R => BUS64353, wr_pred_addr2_L => BUS64363, wr_pred_addr2_R => BUS64371 ); E_DF : Dreg_EDF generic map ( Td_ck_out => 0 ns ) port map( ALU_L => BUS69879, ALU_R => BUS69887, ALUout_L => BUS63281, ALUout_R => BUS63288, Q_addr => BUS31888, Q_data => BUS32179, addr_dcache => BUS70851, clk => clk, data_dcache => BUS70857, reset => reset ); Instruction_decoder : Inst_decoder port map( IR_L => BUS73041, IR_R => BUS73070, Instr_type_L => BUS62147, Instr_type_R => BUS62194, Opcode_L => BUS62201, Opcode_R => BUS62208, Rd_L => BUS62229, Rd_M_L => BUS62236, Rd_M_R => BUS62243, Rd_R => BUS62250, Rs1_L => BUS62257, Rs1_R => BUS62264, Rs2_L => BUS62271, Rs2_R => BUS62278, Subopsw_L => BUS62285, Subopsw_R => BUS62292, imm_L => BUS62303, imm_R => BUS62310, pred_L => BUS72496, pred_R => BUS72507, pred_imm4_L => BUS62339, pred_imm4_R => BUS62382, pred_imm8_L => BUS62385, pred_imm8_R => BUS62393, we_Dcache_L => BUS62405, we_Dcache_R => BUS62412, we_RF_L => BUS62423, we_RF_M_L => BUS62434, we_RF_M_R => BUS62445, we_RF_R => BUS62456, we_pred_L => BUS62467, we_pred_R => BUS62478, wr_pred_addr1_L => BUS62489, wr_pred_addr1_R => BUS62500, wr_pred_addr2_L => BUS62511, wr_pred_addr2_R => BUS62522 ); MUL_DFW : mulpipe port map( I_MULL => BUS64380, I_MULR => BUS64428, MULL => BUS69839, MULR => BUS69845, clk => clk, reset => reset ); MUL_L : mul port map( MulOut => BUS64517, Op1 => BUS71910, Op2 => BUS71933, Opcode => BUS72955, Subop => BUS72341, clk => clk, reset => reset ); MUL_R : mul port map( MulOut => BUS64505, Op1 => BUS71955, Op2 => BUS72010, Opcode => BUS72394, Subop => BUS72370, clk => clk, reset => reset ); pred_DFW : pred_pipereg port map( Data_L => NET29292, Data_R => NET29415, I_8_valid => NET71470, I_Data_L => NET63331, I_bank => BUS71490, I_data_R => NET63337, I_imm8 => BUS71493, I_pred_L => BUS63309, I_pred_R => BUS63316, O_8_valid => NET29486, bank => BUS29446, clk => clk, imm8 => BUS29526, pred_L => BUS69559, pred_R => BUS69565, reset => reset ); pred_DRE : pred_pipereg port map( I_8_valid => NET71232, I_Data_L => Dangling_Input_Signal, I_bank => BUS71303, I_data_R => Dangling_Input_Signal, I_imm8 => BUS71226, I_pred_L => BUS72496, I_pred_R => BUS72507, O_8_valid => NET71311, bank => BUS71452, clk => clk, imm8 => BUS71317, pred_L => BUS62916, pred_R => BUS62923, reset => reset ); pred_EDF : pred_pipereg port map( Data_L => NET63331, Data_R => NET63337, I_8_valid => NET71311, I_Data_L => NET70776, I_bank => BUS71452, I_data_R => NET70782, I_imm8 => BUS71317, I_pred_L => BUS62916, I_pred_R => BUS62923, O_8_valid => NET71470, bank => BUS71490, clk => clk, imm8 => BUS71493, pred_L => BUS63309, pred_R => BUS63316, reset => reset ); SHF_L : sp port map( CLOCK => clk, Data => BUS64708, Opcode => BUS72955, Rs1 => BUS71910, Rs2 => BUS71933, Subop => BUS73301 ); SHF_R : sp port map( CLOCK => clk, Data => BUS64749, Opcode => BUS72394, Rs1 => BUS71955, Rs2 => BUS72010, Subop => BUS73291 ); U1 : DREG_IFDR port map( CLK => clk, IR_L => BUS73041, IR_R => BUS73070, I_IR_L => b, I_IR_L_after => BUS90866, I_IR_R(0) => a(0), I_IR_R(1) => a(1), I_IR_R(2) => a(2), I_IR_R(3) => a(3), I_IR_R(4) => a(4), I_IR_R(5) => a(5), I_IR_R(6) => a(6), I_IR_R(7) => a(7), I_IR_R(8) => a(8), I_IR_R(9) => a(9), I_IR_R(10) => a(10), I_IR_R(11) => a(11), I_IR_R(12) => a(12), I_IR_R(13) => a(13), I_IR_R(14) => a(14), I_IR_R(15) => a(15), I_IR_R(16) => a(16), I_IR_R(17) => a(17), I_IR_R(18) => a(18), I_IR_R(19) => a(19), I_IR_R(20) => a(20), I_IR_R(21) => a(21), I_IR_R(22) => a(22), I_IR_R(23) => a(23), I_IR_R(24) => a(24), I_IR_R(25) => a(25), I_IR_R(26) => a(26), I_IR_R(27) => a(27), I_IR_R(28) => a(28), I_IR_R(29) => a(29), I_IR_R(30) => a(30), I_IR_R(31) => a(31), I_IR_R_after => BUS90894, I_PC_L => BUS32185, I_PC_R => BUS22962, PC_L => BUS72497, PC_R => BUS62222, reset => reset, stall0 => NET71277, stall1 => NET86513 ); U10 : ctrl_unit port map( ALU_L => BUS64804, ALU_R => BUS64818, ALUoutL => BUS69879, ALUoutR => BUS69887, CMPresuL => NET70776, CMPresuR => NET70782, DFW_Instr_type_L => BUS64832, DFW_Instr_type_R => BUS64842, DFW_Opcode_L => BUS64852, DFW_Opcode_R => BUS64862, DFW_PC_L => BUS64872, DFW_PC_R => BUS64882, DFW_Rd_L => BUS90027, DFW_Rd_M_L => BUS4171, DFW_Rd_M_R => BUS69361, DFW_Rd_R => BUS4155, DFW_Rs1_L => BUS69379, DFW_Rs1_R => BUS69389, DFW_Rs2_L => BUS69399, DFW_Rs2_R => BUS69409, DFW_Subopsw_L => BUS69419, DFW_Subopsw_R => BUS69429, DFW_banksel => BUS29446, DFW_cache_L => BUS71108, DFW_cache_R => BUS71108, DFW_data_L => BUS71110, DFW_data_R => BUS71107, DFW_imm_L => BUS69547, DFW_imm_R => BUS69553, DFW_pred_L => BUS69559, DFW_pred_R => BUS69565, DFW_pred_d_L => NET29292, DFW_pred_d_R => NET29415, DFW_valid_L => BUS69765, DFW_valid_R => BUS69771, DFW_we_Dcache_L => BUS69777, DFW_we_Dcache_R => BUS69783, DFW_we_RF_L => BUS4097, DFW_we_RF_M_L => BUS4143, DFW_we_RF_M_R => BUS69797, DFW_we_RF_R => BUS4081, DFW_we_pred_L => BUS71246, DFW_we_pred_R => BUS71248, DFW_wr_pred_addr1_L => BUS29641, DFW_wr_pred_addr1_R => BUS29809, DFW_wr_pred_addr2_L => BUS29629, DFW_wr_pred_addr2_R => BUS29623, DRE_Instr_type_L => BUS62778, DRE_Instr_type_R => BUS62785, DRE_Opcode_L => BUS72955, DRE_Opcode_R => BUS72394, DRE_PC_L => BUS62806, DRE_PC_R => BUS62813, DRE_Rd_L => BUS62820, DRE_Rd_M_L => BUS62827, DRE_Rd_M_R => BUS62834, DRE_Rd_R => BUS62841, DRE_Rs1_L => BUS62848, DRE_Rs1_R => BUS62855, DRE_Rs2_L => BUS62864, DRE_Rs2_R => BUS62874, DRE_Subopsw_L => BUS72341, DRE_Subopsw_R => BUS72370, DRE_banksel => BUS71452, DRE_imm_L => BUS62902, DRE_imm_R => BUS62976, DRE_pred_L => BUS62916, DRE_pred_R => BUS62923, DRE_st_L => BUS62926, DRE_st_R => BUS62932, DRE_unknown => NET62938, DRE_valid_L => BUS62948, DRE_valid_R => BUS62955, DRE_we_Dcache_L => BUS62962, DRE_we_Dcache_R => BUS62969, DRE_we_RF_L => BUS62986, DRE_we_RF_M_L => BUS62996, DRE_we_RF_M_R => BUS63006, DRE_we_RF_R => BUS63016, DRE_we_pred_L => BUS63039, DRE_we_pred_R => BUS63050, DRE_wr_pred_addr1_L => BUS63061, DRE_wr_pred_addr1_R => BUS63072, DRE_wr_pred_addr2_L => BUS63083, DRE_wr_pred_addr2_R => BUS63094, DRMUX1_L => BUS70788, DRMUX1_R => BUS70800, DRMUX2_L => BUS70806, DRMUX2_R => BUS70812, DR_Rs1_L => BUS62525, DR_Rs1_R => BUS62695, DR_Rs2_L => BUS62707, DR_Rs2_R => BUS72956, DR_unknown => NET70818, DR_valid_L => NET70824, DR_valid_R => NET70830, Dcache_we => NET70836, Dcacheout => BUS64771, EDF_Instr_type_L => BUS63105, EDF_Instr_type_R => BUS63133, EDF_Opcode_L => BUS63145, EDF_Opcode_R => BUS63156, EDF_PC_L => BUS63167, EDF_PC_R => BUS63178, EDF_Rd_L => BUS63189, EDF_Rd_M_L => BUS63200, EDF_Rd_M_R => BUS63211, EDF_Rd_R => BUS63222, EDF_Rs1_L => BUS63233, EDF_Rs1_R => BUS63240, EDF_Rs2_L => BUS63247, EDF_Rs2_R => BUS63254, EDF_Subopsw_L => BUS63261, EDF_Subopsw_R => BUS63268, EDF_banksel => BUS71490, EDF_data_L => BUS63281, EDF_data_R => BUS63288, EDF_imm_L => BUS63295, EDF_imm_R => BUS63302, EDF_pred_L => BUS63309, EDF_pred_R => BUS63316, EDF_pred_d_L => NET63331, EDF_pred_d_R => NET63337, EDF_valid_L => BUS64038, EDF_valid_R => BUS64045, EDF_we_Dcache_L => BUS64052, EDF_we_Dcache_R => BUS64059, EDF_we_RF_L => BUS64066, EDF_we_RF_M_L => BUS64075, EDF_we_RF_M_R => BUS64085, EDF_we_RF_R => BUS64095, EDF_we_pred_L => BUS64323, EDF_we_pred_R => BUS64333, EDF_wr_pred_addr1_L => BUS64343, EDF_wr_pred_addr1_R => BUS64353, EDF_wr_pred_addr2_L => BUS64363, EDF_wr_pred_addr2_R => BUS64371, E_st_addr => BUS70851, E_st_data => BUS70857, E_valid_R => NET70900, IR_Instr_type_L => BUS62147, IR_Instr_type_R => BUS62194, IR_Opcode_L => BUS62201, IR_Opcode_R => BUS62208, IR_PC_L => BUS72497, IR_PC_R => BUS62222, IR_Rd_L => BUS62229, IR_Rd_M_L => BUS62236, IR_Rd_M_R => BUS62243, IR_Rd_R => BUS62250, IR_Rs1_L => BUS62257, IR_Rs1_R => BUS62264, IR_Rs2_L => BUS62271, IR_Rs2_R => BUS62278, IR_Subopsw_L => BUS62285, IR_Subopsw_R => BUS62292, IR_banksel => BUS71303, IR_imm_L => BUS62303, IR_imm_R => BUS62310, IR_pred_L => BUS72496, IR_pred_R => BUS72507, IR_pred_d_L => NET62327, IR_pred_d_R => NET62333, IR_pred_imm4_L => BUS62339, IR_pred_imm4_R => BUS62382, IR_pred_imm8_L => BUS62385, IR_pred_imm8_R => BUS62393, IR_we_Dcache_L => BUS62405, IR_we_Dcache_R => BUS62412, IR_we_RF_L => BUS62423, IR_we_RF_M_L => BUS62434, IR_we_RF_M_R => BUS62445, IR_we_RF_R => BUS62456, IR_we_pred_L => BUS62467, IR_we_pred_R => BUS62478, IR_wr_pred_addr1_L => BUS62489, IR_wr_pred_addr1_R => BUS62500, IR_wr_pred_addr2_L => BUS62511, IR_wr_pred_addr2_R => BUS62522, JMP_disp => BUS70910, JMPvalidL => NET70918, JMPvalidR => NET81503, MULDFW_L => BUS69839, MULDFW_R => BUS69845, MULEDF_L => BUS64380, MULEDF_R => BUS64428, MUL_L => BUS64517, MUL_R => BUS64505, MULpipe_L => BUS70975, MULpipe_R => BUS70981, RF_Rd_L => BUS71069, RF_Rd_M => BUS71088, RF_Rd_R => BUS71098, RF_data_L => BUS71114, RF_data_M => BUS71124, RF_data_R => BUS71134, RF_we_L => NET71144, RF_we_M => NET71154, RF_we_R => NET71164, SHF_L => BUS64708, SHF_R => BUS64749, chpr_imm4 => BUS71174, chpr_valid => NET71184, pred_imm8 => BUS71226, pred_we8b => NET71232, pred_we_L => NET71257, pred_we_R => NET71267, reset => reset, stallL => NET71277, stallR => NET86513 ); U11 : DREG_IFDR port map( CLK => clk, IR_L => BUS73275, IR_R => BUS73281, I_IR_L => BUS73041, I_IR_L_after => BUS90866, I_IR_R => BUS73070, I_IR_R_after => BUS90894, I_PC_L => b, I_PC_R(0) => a(0), I_PC_R(1) => a(1), I_PC_R(2) => a(2), I_PC_R(3) => a(3), I_PC_R(4) => a(4), I_PC_R(5) => a(5), I_PC_R(6) => a(6), I_PC_R(7) => a(7), I_PC_R(8) => a(8), I_PC_R(9) => a(9), I_PC_R(10) => a(10), I_PC_R(11) => a(11), I_PC_R(12) => a(12), I_PC_R(13) => a(13), I_PC_R(14) => a(14), I_PC_R(15) => a(15), I_PC_R(16) => a(16), I_PC_R(17) => a(17), I_PC_R(18) => a(18), I_PC_R(19) => a(19), I_PC_R(20) => a(20), I_PC_R(21) => a(21), I_PC_R(22) => a(22), I_PC_R(23) => a(23), I_PC_R(24) => a(24), I_PC_R(25) => a(25), I_PC_R(26) => a(26), I_PC_R(27) => a(27), I_PC_R(28) => a(28), I_PC_R(29) => a(29), I_PC_R(30) => a(30), I_PC_R(31) => a(31), reset => reset, stall0 => GND, stall1 => GND ); U12 : Subop13 port map( Inst_L => BUS73275, Inst_R => BUS73281, subop_L => BUS73301, subop_R => BUS73291 ); U13 : dcaceh_tmp port map( Dcacheout => BUS64771, Raddr => BUS31888, Waddr => BUS31888, Wdata => BUS32179, we => NET70836 ); U14 : ALU64 port map( ALUout => BUS64804, Op1 => BUS71910, Op2 => BUS71933, Opcode => BUS72955, SubOP => BUS72341 ); U15 : ALU64 port map( ALUout => BUS64818, Op1 => BUS71955, Op2 => BUS72010, Opcode => BUS72394, SubOP => BUS72370 ); U2 : pred_reg_v2 port map( imm8 => BUS29526, out_L => NET62327, out_R => NET62333, rd_addr_L => BUS72496, rd_addr_R => BUS72507, rd_banksel => BUS71303, reset => reset, we_8b => NET29486, we_L => NET71257, we_R => NET71267, wr_addr1_L => BUS29641, wr_addr1_R => BUS29809, wr_addr2_L => BUS29629, wr_addr2_R => BUS29623, wr_banksel => BUS29446, wr_d1_L => NET29292, wr_d1_R => NET29415, wr_d2_L => NET29295, wr_d2_R => NET29405 ); U3 : PC_gen port map( I_PC => BUS72497, I_PC_4 => BUS62222, JMPvalidL => NET70918, JMPvalidR => NET81503, PC_4out => BUS22962, PCout => BUS32185, clk => clk, disp => BUS70910, reset => reset, stallL => NET71277, stallR => NET86513 ); U4 : I_Cache port map( instr2(0) => a(0), instr2(1) => a(1), instr2(2) => a(2), instr2(3) => a(3), instr2(4) => a(4), instr2(5) => a(5), instr2(6) => a(6), instr2(7) => a(7), instr2(8) => a(8), instr2(9) => a(9), instr2(10) => a(10), instr2(11) => a(11), instr2(12) => a(12), instr2(13) => a(13), instr2(14) => a(14), instr2(15) => a(15), instr2(16) => a(16), instr2(17) => a(17), instr2(18) => a(18), instr2(19) => a(19), instr2(20) => a(20), instr2(21) => a(21), instr2(22) => a(22), instr2(23) => a(23), instr2(24) => a(24), instr2(25) => a(25), instr2(26) => a(26), instr2(27) => a(27), instr2(28) => a(28), instr2(29) => a(29), instr2(30) => a(30), instr2(31) => a(31), address => BUS32185, instr1 => b, instr3 => BUS90866, instr4 => BUS90894, oen => VCC ); U5 : pred_IFDR port map( bank_sel => BUS71303, chpr_valid => NET71184, clk => clk, imm4 => BUS71174, reset => reset ); U6 : regfile port map( rd_a_L1 => BUS62257, rd_a_L2 => BUS62271, rd_a_R1 => BUS62264, rd_a_R2 => BUS62278, rd_q_L1 => BUS62525, rd_q_L2 => BUS62707, rd_q_R1 => BUS62695, rd_q_R2 => BUS72956, we_L => NET71144, we_M => NET71154, we_R => NET71164, wr_a_L => BUS71069, wr_a_M => BUS71088, wr_a_R => BUS71098, wr_d_L => BUS71114, wr_d_M => BUS71124, wr_d_R => BUS71134 ); U7 : mulpipe port map( I_MULL => BUS70975, I_MULR => BUS70981, MULL => BUS64380, MULR => BUS64428, clk => clk, reset => reset ); U8 : my_inv port map( I => NET29292, O => NET29295 ); U9 : my_inv port map( I => NET29415, O => NET29405 ); ---- Power , ground assignment ---- VCC <= VCC_CONSTANT; GND <= GND_CONSTANT; ---- Dangling input signal assignment ---- Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT; end struc_PLX;