--
--  File: MUL.vhd
--  created by Design Wizard: 01/14/02 05:30:31
--

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {MUL} architecture {MUL_bh}}

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity MUL is
	port (
		Op1: in STD_LOGIC_VECTOR (63 downto 0);
		Op2: in STD_LOGIC_VECTOR (63 downto 0);
		Opcode: in STD_LOGIC_VECTOR (5 downto 0);
		Subop: in STD_LOGIC_VECTOR (7 downto 0);   
		clk:   in STD_LOGIC;		   
		reset : in STD_LOGIC;
		MulOut: out STD_LOGIC_VECTOR (63 downto 0)
	);
end MUL;

--}} End of automatically maintained section

architecture MUL_bh of MUL is
begin
	Multiply: process (	clk,reset )
	variable stage1, stage2, stage3 : STD_LOGIC_VECTOR (63 downto 0);
	variable tmp : STD_LOGIC_VECTOR (31 downto 0);
	begin						 
		if reset = '0' then
			--stage1 := x"0000000000000000";
			stage2 := x"0000000000000000";
			stage3 := x"0000000000000000";
		else
			if clk'event and clk='1' then
				stage3 := stage2;
				--stage2 := stage1;
				case Subop(7 downto 2) is
					when "000000" => -- MUL.odd
					tmp := STD_LOGIC_VECTOR(signed(Op1(31 downto 16)) * signed(Op2(31 downto 16)));
					stage2(31 downto 0) := tmp;
					tmp := STD_LOGIC_VECTOR(signed(Op1(63 downto 48)) * signed(Op2(63 downto 48)));
					stage2(63 downto 32) := tmp;
					when "000001" => -- MUL.even
					tmp := STD_LOGIC_VECTOR(signed(Op1(15 downto 0)) * signed(Op2(15 downto 0)));
					stage2(31 downto 0) := tmp;
					tmp := STD_LOGIC_VECTOR(signed(Op1(47 downto 32)) * signed(Op2(47 downto 32)));
					stage2(63 downto 32) := tmp;
					when "000100" => --	Pmulshr.0.a
					when "000101" => -- Pmulshr.8.a
					when "000110" => -- Pmulshr.15.a
					when "000111" => -- Pmulshr.16.a
					when "001000" => --	Pmulshr.0.l
					when "001001" => -- Pmulshr.8.l
					when "001010" => -- Pmulshr.15.l
					when "001011" => -- Pmulshr.16.l
					when others =>
		  				assert (false) -- assert always
                			report "Invalid SubOP for MUL instructions!!"
                			severity WARNING;
          		end case;
			end if;
		end if;
		Mulout <= stage3;
	end process;
end MUL_bh;