--
--  File: I_Cache.vhd
--  created by Design Wizard: 12/13/01 02:02:59
--

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {I_Cache} architecture {I_Cache_bh}}

library IEEE,std;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;	 
use IEEE.std_logic_textio.all;
use std.textio.all;

entity I_Cache is  
	generic (		   
		prop:	time := 2 ns);
	port (
		address: in STD_LOGIC_VECTOR (31 downto 0);
		oen: in STD_LOGIC;
		instr1: out STD_LOGIC_VECTOR (31 downto 0);
		instr2: out STD_LOGIC_VECTOR (31 downto 0);
		instr3: out STD_LOGIC_VECTOR (31 downto 0);	  
		instr4: out STD_LOGIC_VECTOR (31 downto 0)
	);
end I_Cache;

--}} End of automatically maintained section

architecture I_Cache_bh of I_Cache is
	type cache is array(0 to (1024/4-1)) of std_logic_vector(31 downto 0);
	signal imem :	cache;
--	signal i	:	integer;
	signal tmp_inst1, tmp_inst2:std_logic_vector(63 downto 0);
	signal instrs1, instrs2    :std_logic_vector(63 downto 0);
	signal pre_inst1:std_logic_vector(63 downto 0);	 
	signal pre_inst2:std_logic_vector(63 downto 0);
    file   instr_image: TEXT is in "fibo.in"; 
	--file   instr_image: TEXT is in "faxpy.in"; 
begin
  -- <<enter your statements here>> 
  	instr1 <= instrs1(31 downto 0);
  	instr2 <= instrs1(63 downto 32);		   
	instr3 <= instrs2(31 downto 0);
  	instr4 <= instrs2(63 downto 32);
  	process	
	  variable imem_ini: boolean := TRUE;
	  variable i       : integer := 0;
      variable li      : LINE;
	  variable instr_in: std_logic_vector(31 downto 0);
	begin
	  if (imem_ini) then
		  i := 0;
		  -- wait for 0 ns;
		  while	(i < (1024/4)) loop	
			  if ENDFILE(instr_image) then 
				  imem(i) <= "00000000000000000000000000000000";
			  else				  
				  READLINE(instr_image,li);
				  READ(li,instr_in);
				  imem(i) <= instr_in;
			  end if; 
			  i := i+1;
			--  wait for 0 ns;
		  end loop;
		  --WRITE("output","Loading instruction memory image...");
		  -- READLINE(instr_image,li);
		  imem_ini := FALSE; 
	  else
		  wait;
	  end if;
	end process;
	tmp_inst1 <= pre_inst1(63 downto 0) when oen='1' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
	instrs1 <= tmp_inst1;
	tmp_inst2 <= pre_inst2(63 downto 0) when oen='1' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
	instrs2 <= tmp_inst2;
	process 
	begin
          wait until address'EVENT;
          pre_inst1(63 downto 32) <= imem(TO_INTEGER(UNSIGNED(address)/4)+1) after prop-1 ns;
          pre_inst1(31 downto 0) <= imem(TO_INTEGER(UNSIGNED(address)/4)) after prop-1 ns;
		  pre_inst2(63 downto 32) <= imem(TO_INTEGER(UNSIGNED(address)/4)+3) after prop-1 ns;
          pre_inst2(31 downto 0) <= imem(TO_INTEGER(UNSIGNED(address)/4)+2) after prop-1 ns;
	end process;	   	  
  
end I_Cache_bh;