--
--  File: Ctrl_reg.vhd
--  created by Design Wizard: 12/23/01 02:34:41
--

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {Ctrl_reg} architecture {struc_Ctrlreg}}

library IEEE;
use IEEE.std_logic_1164.all;

entity Ctrl_reg is
	port (													  
-- input ports
				clk: in STD_LOGIC;
				reset: in STD_LOGIC;
	-- Left part
				I_Opcode_L : in STD_LOGIC_VECTOR (5 downto 0);
				I_Subopsw_L: in STD_LOGIC_VECTOR (7 downto 0);
				I_Rd_L   : in STD_LOGIC_VECTOR (4 downto 0);
				I_Rs1_L  : in STD_LOGIC_VECTOR (4 downto 0);
                I_Rs2_L  : in STD_LOGIC_VECTOR (4 downto 0);
                I_imm_L  : in STD_LOGIC_VECTOR (63 downto 0);
                I_we_RF_L: in STD_LOGIC_VECTOR (0 downto 0);
				I_we_Dcache_L: in STD_LOGIC_VECTOR (0 downto 0);
                I_we_RF_M_L  : in STD_LOGIC_VECTOR (0 downto 0);
                I_Rd_M_L     : in STD_LOGIC_VECTOR (4 downto 0);		
                -- pred file control signals 
				I_wr_pred_addr1_L: in std_logic_vector (2 downto 0);
				I_wr_pred_addr2_L: in std_logic_vector (2 downto 0);
				I_we_pred_L : in STD_LOGIC_VECTOR (0 downto 0);	  
				-- valid bits
				I_valid_L  : in STD_LOGIC_VECTOR (0 downto 0);
				-- pipelined PC
				I_PC_L     : in STD_LOGIC_VECTOR (31 downto 0);	 
				-- pipelined instruction type indicator
				I_Instr_type_L: in STD_LOGIC_VECTOR (8 downto 0);
				-- imm to PC for branch control needed to be added
					
	-- Right part			               
                I_Opcode_R : in STD_LOGIC_VECTOR (5 downto 0);
                I_Subopsw_R: in STD_LOGIC_VECTOR (7 downto 0);
                I_Rd_R   : in STD_LOGIC_VECTOR (4 downto 0);
                I_Rs1_R  : in STD_LOGIC_VECTOR (4 downto 0);
                I_Rs2_R  : in STD_LOGIC_VECTOR (4 downto 0);
                I_imm_R  : in STD_LOGIC_VECTOR (63 downto 0);
                I_we_RF_R: in STD_LOGIC_VECTOR (0 downto 0);
				I_we_Dcache_R: in STD_LOGIC_VECTOR (0 downto 0);
                I_we_RF_M_R  : in STD_LOGIC_VECTOR (0 downto 0);
                I_Rd_M_R     : in STD_LOGIC_VECTOR (4 downto 0);	
                -- pred file control signals
				I_wr_pred_addr1_R: in std_logic_vector (2 downto 0);   
				I_wr_pred_addr2_R: in std_logic_vector (2 downto 0);
				I_we_pred_R : in STD_LOGIC_VECTOR (0 downto 0);
				-- valid bits
				I_valid_R  : in STD_LOGIC_VECTOR (0 downto 0);	
				-- pipelined PC
				I_PC_R     : in STD_LOGIC_VECTOR (31 downto 0);	
				-- pipelined instruction type indicator
				I_Instr_type_R: in STD_LOGIC_VECTOR (8 downto 0);
                -- imm to PC for branch control needed to be added
				
-- Output ports
	-- left part
				Opcode_L : out STD_LOGIC_VECTOR (5 downto 0);
				Subopsw_L: out STD_LOGIC_VECTOR (7 downto 0);
				Rd_L   : out STD_LOGIC_VECTOR (4 downto 0);
				Rs1_L  : out STD_LOGIC_VECTOR (4 downto 0);
        		Rs2_L  : out STD_LOGIC_VECTOR (4 downto 0);
                imm_L  : out STD_LOGIC_VECTOR (63 downto 0);
                we_RF_L: out STD_LOGIC_VECTOR (0 downto 0);	 
				we_Dcache_L: out STD_LOGIC_VECTOR (0 downto 0);
                we_RF_M_L  : out STD_LOGIC_VECTOR (0 downto 0);
                Rd_M_L     : out STD_LOGIC_VECTOR (4 downto 0);	
                -- pred file control signals
				wr_pred_addr1_L: out std_logic_vector (2 downto 0);
				wr_pred_addr2_L: out std_logic_vector (2 downto 0);	
				we_pred_L : out STD_LOGIC_VECTOR (0 downto 0);
				-- valid bits
				valid_L  : out STD_LOGIC_VECTOR (0 downto 0);  
				-- pipelined PC
				PC_L     : out STD_LOGIC_VECTOR (31 downto 0); 
				-- pipelined instruction type indicator
				Instr_type_L: out STD_LOGIC_VECTOR (8 downto 0);
                -- imm to PC for branch control needed to be added
    -- right part            
				Opcode_R : out STD_LOGIC_VECTOR (5 downto 0);
                Subopsw_R: out STD_LOGIC_VECTOR (7 downto 0);
                Rd_R   : out STD_LOGIC_VECTOR (4 downto 0);
                Rs1_R  : out STD_LOGIC_VECTOR (4 downto 0);
                Rs2_R  : out STD_LOGIC_VECTOR (4 downto 0);
                imm_R  : out STD_LOGIC_VECTOR (63 downto 0);
                we_RF_R: out STD_LOGIC_VECTOR (0 downto 0);
				we_Dcache_R: out STD_LOGIC_VECTOR (0 downto 0);
                we_RF_M_R  : out STD_LOGIC_VECTOR (0 downto 0);
                Rd_M_R     : out STD_LOGIC_VECTOR (4 downto 0);	
                -- pred file control signals 
				wr_pred_addr1_R: out std_logic_vector (2 downto 0);	
				wr_pred_addr2_R: out std_logic_vector (2 downto 0);	
				we_pred_R : out STD_LOGIC_VECTOR (0 downto 0); 
				-- valid bits
				valid_R  : out STD_LOGIC_VECTOR (0 downto 0);  
				-- pipelined PC
				PC_R     : out STD_LOGIC_VECTOR (31 downto 0);
				-- pipelined instruction type indicator
				Instr_type_R: out STD_LOGIC_VECTOR (8 downto 0)
                -- imm to PC for branch control needed to be added
	);
end Ctrl_reg;

--}} End of automatically maintained section

architecture struc_Ctrlreg of Ctrl_reg is

   component DFFR       
   GENERIC(
      width : integer := 64
   );
   PORT(
      CK_L : IN     std_logic  ;
      D    : IN     std_logic_vector (width-1 DOWNTO 0) ;
      RS_L : IN     std_logic  ;
      Q    : OUT    std_logic_vector (width-1 DOWNTO 0)
   );
   end component;

begin
   -- <<enter your statements here>>	  
   regOpcode_L: DFFR
   GENERIC map(
      width => 6 )
   port map(
      CK_L => clk,
      D    => I_Opcode_L,
      RS_L => reset,
      Q    => Opcode_L);
   
   regOpcode_R: DFFR
   GENERIC map(
      width => 6 )
   port map(
      CK_L => clk,
      D    => I_Opcode_R,
      RS_L => reset,
      Q    => Opcode_R);   
	  
   regSubopsw_L: DFFR
   GENERIC map(
      width => 8 )
   port map(
      CK_L => clk,
      D    => I_Subopsw_L,
      RS_L => reset,
      Q    => Subopsw_L); 
	 
   regSubopsw_R: DFFR
   GENERIC map(
      width => 8 )
   port map(
      CK_L => clk,
      D    => I_Subopsw_R,
      RS_L => reset,
      Q    => Subopsw_R); 
   
   regRd_L: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rd_L,
      RS_L => reset,
      Q    => Rd_L);    
	  
   regRd_R: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rd_R,
      RS_L => reset,
      Q    => Rd_R);    
	 
   regRs1_L: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rs1_L,
      RS_L => reset,
      Q    => Rs1_L);    	 
	
   regRs1_R: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rs1_R,
      RS_L => reset,
      Q    => Rs1_R);    	  
	  
   regRs2_L: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rs2_L,
      RS_L => reset,
      Q    => Rs2_L);    	 
	
   regRs2_R: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rs2_R,
      RS_L => reset,
      Q    => Rs2_R);    
	  
   regimm_L: DFFR
   GENERIC map(
      width => 64 )
   port map(
      CK_L => clk,
      D    => I_imm_L,
      RS_L => reset,
      Q    => imm_L);
	  
   regimm_R: DFFR
   GENERIC map(
      width => 64 )
   port map(
      CK_L => clk,
      D    => I_imm_R,
      RS_L => reset,
      Q    => imm_R);  
	  
   regwe_RF_L: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_RF_L,
      RS_L => reset,
      Q    => we_RF_L);
	  
   regwe_RF_R: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_RF_R,
      RS_L => reset,
      Q    => we_RF_R);
	  
   regwe_RF_M_L: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_RF_M_L,
      RS_L => reset,
      Q    => we_RF_M_L);
	  
   regwe_Dcache_L: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_Dcache_L,
      RS_L => reset,
      Q    => we_Dcache_L); 
	  
   regRd_M_L: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rd_M_L,
      RS_L => reset,
      Q    => Rd_M_L);		   
	  
   regwe_RF_M_R: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_RF_M_R,
      RS_L => reset,
      Q    => we_RF_M_R);
	  
   regwe_Dcache_R: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_Dcache_R,
      RS_L => reset,
      Q    => we_Dcache_R); 
	  
   regRd_M_R: DFFR
   GENERIC map(
      width => 5 )
   port map(
      CK_L => clk,
      D    => I_Rd_M_R,
      RS_L => reset,
      Q    => Rd_M_R);
	  
   regwr_pred_addr1_L: DFFR
   GENERIC map(
      width => 3 )
   port map(
      CK_L => clk,
      D    => I_wr_pred_addr1_L,
      RS_L => reset,
      Q    => wr_pred_addr1_L);		   	 
	  
   regwr_pred_addr2_L: DFFR
   GENERIC map(
      width => 3 )
   port map(
      CK_L => clk,
      D    => I_wr_pred_addr2_L,
      RS_L => reset,
      Q    => wr_pred_addr2_L);		   
	
   regwr_pred_addr1_R: DFFR
   GENERIC map(
      width => 3 )
   port map(
      CK_L => clk,
      D    => I_wr_pred_addr1_R,
      RS_L => reset,
      Q    => wr_pred_addr1_R);		   	 
	  
   regwr_pred_addr2_R: DFFR
   GENERIC map(
      width => 3 )
   port map(
      CK_L => clk,
      D    => I_wr_pred_addr2_R,
      RS_L => reset,
      Q    => wr_pred_addr2_R);		   
	  
   regwe_pred_L: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_pred_L,
      RS_L => reset,
      Q    => we_pred_L);		   
	
   regwe_pred_R: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_we_pred_R,
      RS_L => reset,
      Q    => we_pred_R);
	  
   regvalid_L: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_valid_L,
      RS_L => reset,
      Q    => valid_L);		   
	
   regvalid_R: DFFR
   GENERIC map(
      width => 1 )
   port map(
      CK_L => clk,
      D    => I_valid_R,
      RS_L => reset,
      Q    => valid_R);	  	
	  
   regPC_L: DFFR
   GENERIC map(
      width => 32 )
   port map(
      CK_L => clk,
      D    => I_PC_L,
      RS_L => reset,
      Q    => PC_L);	
	  
   regPC_R: DFFR
   GENERIC map(
      width => 32 )
   port map(
      CK_L => clk,
      D    => I_PC_R,
      RS_L => reset,
      Q    => PC_R);	
	  
   regInstr_type_L: DFFR
   GENERIC map(
      width => 9 )
   port map(
      CK_L => clk,
      D    => I_Instr_type_L,
      RS_L => reset,
      Q    => Instr_type_L);	   
   
   regInstr_type_R: DFFR
   GENERIC map(
      width => 9 )
   port map(
      CK_L => clk,
      D    => I_Instr_type_R,
      RS_L => reset,
      Q    => Instr_type_R);
	  
end struc_Ctrlreg;