-- TITLE:
-----------------------------------------------------------------
-- test code for the ALU:(leaf cell, lowest hierarchy)         --
-----------------------------------------------------------------
-- Description: Crappy quick tester code   --
--              								   --
-----------------------------------------------------------------
-- Course: Computer Architecture Project #2                    --
-----------------------------------------------------------------
-- Date | Begin: 12.05.2001                                    --
--      | End  : 12.05.2001                                    --
-----------------------------------------------------------------
-- Additional Comments:                                        --
--                                                             --
-----------------------------------------------------------------

-- ACCESSING DESIGN LIBRARIES and PACKAGES:
-------------------------------------------

---Library Clause: (Makes the written libraries visible to the design unit)
library ieee,work;
----work is working(design) library (there can be only 1!!)

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------------

--ENTITY DECLARATION and PORT MAP: (Interface of design unit to external env.)
----------------------------------

entity ALU64_tester is       -- ALU64_tester: name of entity
                      -- entity name must be unique in the design library!!
  port (UP      :  out  std_logic_vector(63 downto 0); -- UP i/p of ALU
        DOWN    :  out  std_logic_vector(63 downto 0); -- DOWN i/p of ALU
        SubOP   :  out  std_logic_vector(7 downto 0);  -- SubOP portion (7:0) of 32 bit instr.
        ALUfunc :  out  std_logic_vector(5 downto 0);  -- comes from controller, BITWIDTH arbitrarily assigned for now!!
        ALUout  :  in   std_logic_vector(63 downto 0)); -- ALU64 o/p

end ALU64_tester;
------------------------------------------------------------------------------

--ARCHITECTURE BODY: (Internal details, function of block)
--------------------

architecture testbench of ALU64_tester is 

constant period : time := 100 ns;
signal int_ALUout : integer := 0;
signal int_UP : integer := 0;
signal int_DOWN : integer := 0;
signal ALUtestgoes : boolean := TRUE; 

begin -- of architecture

-- lets use some type conversion and type casting for our lazy well beings
--so we can read the integer values when we add UP + DOWN = ALUout

int_ALUout <= to_integer(signed(ALUout)); -- get the integer value whenever ALUout changes
UP <= std_logic_vector(to_signed(int_UP, 64)); -- convert to std_logic value whenever UP changed
DOWN <= std_logic_vector(to_signed(int_DOWN, 64)); --same for DOWN

  ALUtest: process 

  --- Process Declarations:
  variable hexvar : unsigned(63 downto 0) := (others => '0');
  begin --of process
    ALUfunc <= "110000"; --add my man
    SubOP <= "00000011"; --add 8 byte = full word
    int_UP <= 15;
    int_DOWN <= 32;
    wait for period;
    int_UP <= -99;
    wait for period;
    -- do some subword parallel stuff, now define as hex
    hexvar := X"0011_AAAA_3524_4523";
    int_UP <= to_integer(hexvar);
    hexvar :=  X"7936_4258_0000_1111";
    int_DOWN <= to_integer(hexvar);
    SubOP <= "00000001";
    wait for period;

    ALUfunc <= "001000"; -- compare my dear
    SubOP <= "XXXX0000"; -- cmp.eq
    int_UP <= 10;
    int_DOWN <= -10;
    wait for period;
    SubOP <= "XXXX0101"; -- cmp.ge   
    int_UP <= -8;
    int_DOWN <= 764;
    wait for period;
    SubOP <= "XXXX1001"; -- cmp.geu   
    int_UP <= -8;
    int_DOWN <= 764;
    wait for period;
    int_DOWN <= -8;
    int_UP <= 764;
    wait for period;
    int_DOWN <= -8;
    int_UP <= -764;
    wait for period;
    int_DOWN <= 8;
    int_UP <= 764;
    wait for period;



    ALUtestgoes <= FALSE; -- test finishes    
  end process ALUtest; --EOProcess

assert (ALUtestgoes)
      report "test finished"
      severity FAILURE;      

end testbench; --EOArchitecture